1. Field of the Invention
This invention relates to a clock distribution system for reducing CPU to CPU clock skew in a dual sided tightly coupled system.
2. Description of the Related Art
In a tightly coupled multi-processor system, all processors and the main memory storage run on clocks derived from the same oscillator. FIG. 1 illustrates a tightly coupled multi-processor system. Side 1 of the system comprises a local oscillator 10 providing a local clock on line 12 and a remote clock on line 11. The local clock is connected to the clock controller 13. The clock controller 13 distributes the clock via line to the frame distribution unit 16 which provides the clock to the master storage unit 21. Clock controller also distributes the clock via line 14 to delay 17 which then provides the clock via line 18 to CPU 20. Side 2 of the system comprises a local oscillator 30 which provides a remote clock on line 31 and a local clock on line 32. The local clock of oscillator 30 is connected to clock controller 33 which distributes the clock via line 35 to frame distribution unit 36 and then via line 39 to the master storage unit 41. The clock is also provided via line 34 to delay 37 which provides the clock via line 38 to CPU 40. Oscillator 10's remote clock is connected via line 11 to the clock controller 33 of side 2. Oscillator 30's remote clock is connected to clock controller 13 on side 1 by line 31. Configuration processor 9 controls the configuration of the tightly coupled system by providing to clock controller 13 a local clock selection signal LCL1 on line 22 and a remote clock selection signal RMT1 on lines 23 and by providing to clock controller 33 a local clock selection signal LCL2 on line 42 and a remote clock selection signal RMT2 on line 43.
Where both sides of the system are to operate independently, then configuration processor 9 provides the local clock selection signals LCL1 and LCL2 on lines 22 and 42 to clock controllers 13 and 33, respectively. Under this condition, side 1 will use the local clock of oscillator 10 and side 2 will use the local clock of oscillator 30.
Where both sides of the system are to operate using oscillator 10, then the configuration processor 9 will provide a local clock selection signal LCL1 22 to clock controller 13 and a remote control selection signal RMT2 on line 43 to clock controller 33. In this configuration the remote clock of local oscillator 10 will be used by side 2 and the local clock of oscillator 10 will be used by side 1.
Typically, the clocks are cross coupled immediately after the oscillators because of the physical distances of the frames that house the various units comprising the systems. The master storage unit clock is sent to the frame distribution unit and therefrom to the master storage units. The clock for the CPU is delayed to match the delay in the clock reaching the memory storage unit on the same side of the system signal. Since the master storage unit is far away from the central processing unit, the delay to match the master storage unit clock is large. Further tuning errors, cable and processing variations will cause the clocks to be skewed between the central processing units even though a delay has been used to compensate for the time difference between the CPU and memory storage unit on each side of the system. It is desirable to minimize the clock skew between the central processing units on the two sides of the system.